Design-Reuse

Six DDR Protocols in one PHY - Not for Softies!

With the maximum speed topping out at 1066 Mb/s, mobile applications are driving the DDR roadmap to lower power. This has resulted in a number of different protocols and standards, including: LPDDR2, ...
EDN

DDR PHY Interface Spec

The specification, available for download at DDR is being developed by expert contributors from recognized leaders in the semiconductor, IP and electronic design automation (EDA) industries, including ...
EDN

ESC – New Synopsys Universal DDR Controllers Improve Performance and Reduce Cost of Embedded DRAM Interfaces

Mountain View, Calif. – Synopsys, Inc. today announced the availability of the high-performance DesignWare Universal DDR Protocol and Memory Controllers, both supporting the DDR2, DDR3, Mobile DDR and ...
Design-Reuse

Toshiba Delivers DFI-Compatible DDR PHY to Speed Custom SoC Memory System Designs

New PHY Interoperates with Denali DDR Controller for Reduced Development Costs and Accelerated Time-to-Market PALO ALTO, Calif. -- Nov. 13, 2007 -- Denali Software, Inc., today announced the ...